The present invention relates to semiconductor integrated circuits and more particularly to calibration of a mask signal used to qualify a DQS strobe signal received by a memory controller from a memory device.
Certain types of memory devices utilize a bi-directional data strobe signal (DQS) having edges that are aligned relative to changes in read or write data. A double data rate (DDR) dynamic random access memory (DRAM) transfers data on each rising and falling edge of the DQS signal. A DDR DRAM therefore transfers two data words per clock cycle.
A memory controller is often used to coordinate the transfer of data to and from a memory device, such as a DDR DRAM. The memory controller provides a local clock signal to the memory device for synchronizing read and write operations. During write operations, the memory controller transmits the DQS signal with the write data to the memory device. During read operations, the memory device transmits the DQS signal with the read data to the memory controller. When the memory bus is idle neither the memory controller nor the memory device drives the DQS signal line, and the DQS signal has an invalid, tri-state logic level. When driven, the DQS signal has predefined phase constraints with respect to the local clock signal provided by the memory controller.
During read operations, the memory controller uses the DQS signal for determining when the read data is valid and can therefore be latched. However, the memory controller can look at the DQS signal only when the DQS signal is valid (i.e., not tri-stated). When the DQS signal is tri-stated, a typical memory controller will mask the DQS signal with a mask signal in order to prevent an unknown state from being detected. When the DQS signal becomes valid, the mask signal is disabled and the next transition in the unmasked DQS signal indicates read data is available. The process of masking the DQS signal is sometimes referred to as xe2x80x9cDQS qualificationxe2x80x9d. In order to maximize the size of the read data capture window, it is preferable to disable the masking of the DQS signal in the middle of the preamble phase of the DQS signal waveform. The preamble phase begins when the DQS signal becomes valid and ends with the next transition in the DQS signal.
One method of controlling disablement of the DQS mask after issuing a read command is to disable the mask at a predetermined time delay relative to the memory controller""s local clock signal, which has a predetermined phase relationship with the DQS signal. This time delay is determined based on signal delays and operating conditions that are estimated during the design process. However, this predetermined masking delay requires a large timing margin due to differences between the estimated signal delays and actual signal delays in a particular device. These differences can be caused by input/output (I/O) pad delay variations, power supply fluctuations, process variations, temperature variations and variations in the clock input-to-DQS signal output characteristics of the memory device, for example. As a result, the phase relationship between the memory controller""s local clock signal and the DQS signal can vary from one device to the next and can change over time. The added timing margin within the predetermined, fixed masking delay sets an unnecessary limit on the operating speed of the memory controller.
Improved memory controller circuits are therefore desired that are capable of calibrating the masking delay for the particular integrated circuit or printed circuit board (PCB) in which the controller is used.
One embodiment of the present invention is directed to a method of calibrating a mask signal which is used for masking a data strobe signal that is received from a memory device with read data. According to the method, one or more read operations are performed with the memory device, and the data strobe signal is sampled at a plurality of different time delays relative to a local clock signal to produce a plurality of data strobe sample values. The plurality of data strobe sample values are searched to identify a temporal location within a preamble phase of the data strobe sample values and one of the time delays that corresponds to the temporal location. A delay at which the mask signal is disabled in response to a read operation is then set relative to the local clock signal based on the time delay corresponding to the temporal location.
Another embodiment of the present invention is directed to a read data strobe qualification circuit, which includes a data strobe input, a mask disable control input, a programmable delay line, a data strobe mask circuit, a data strobe capture circuit, a memory device and a control circuit. The programmable delay line is coupled to the mask disable control input and has a delayed mask control output. The data strobe mask circuit has a first input coupled to the data strobe input, a second input coupled to the delayed mask control output and a masked data strobe output. The data strobe capture circuit has a data input coupled to the data strobe input, a capture control input coupled to the delayed mask control output, and a captured data strobe output. The memory device is coupled to the captured data strobe output, and the control circuit is coupled in a feedback loop from the memory device to a delay control input of the programmable delay line.